A variety of techniques have been developed to increase the overall processing speed of computer systems. While improvements in integrated circuit processing technologies such as sub-micron processing capabilities have made it possible to dramatically increase the speed of the integrated circuitry itself, other developments in the architectures and bus transfer mechanisms of computer systems have also led to improvements in performance. Exemplary developments include the incorporation of cache memory subsystems as well as code pre-fetching mechanisms within computer systems.
One source of performance degradation is the refresh requirement of the memory. All dynamic random access memory (DRAM) chips, including synchronous DRAM (SDRAM or SynchDRAM) chips, store information in integrated circuits containing capacitors. Because capacitors lose their charge (or leak) over time, computer systems must include logic to refresh (or re-charge) these integrated circuits periodically. Without constant refreshing, DRAM loses any information stored in it--as it does when the computer is turned off or the power fails.
The frequency with which refresh must occur depends on the silicon technology used to manufacture the memory chip and the design of the memory cell itself. An exemplary SDRAM chip is Micron Technology's 64M SDRAM which requires refresh every 64 milliseconds (or every 64 million cycles at 100 MHz clock frequency). Refresh happens by row. The exemplary SDRAM has a counter for each bank which represents the current row in that bank that is next in line to be refreshed. On each refresh operation, the row indicated by the counter will be refreshed and the counter will increment to the next row. A refresh operation must be executed for every row in the SDRAM and at the appropriate frequency. Therefore, the exemplary SDRAM with 4,096 rows will require 4,096 refreshes with each row being refreshed every 64 milliseconds.
While a refresh operation is taking place, the portion of memory undergoing refresh cannot be accessed by the processor. Therefore, any memory requests for data stored in that memory must be stalled. Typically, each portion of memory is refreshed once or multiple times at pre-defined intervals, depending on the required refresh frequency and the number of rows per bank. However, a fixed refresh interval results in times where portions of the memory are not busy yet it is not time for a refresh and other times when portions of the memory are busy or in demand but requests to those portions must be stalled in order to refresh.
Accordingly, there is a need for an improved more efficient refresh mechanism which can opportunistically utilize idle memory cycles to perform a refresh and increase memory access performance by reducing the occurrences of the situation where requests to the memory must be stalled in order to refresh.